Contemporary fused-multiply-add Floating Point Units usually comprise an incrementer and an end-around-carry adder whose outputs are fed into a normalization shifter. In high frequency floating point units, these parts are often timing critical. This is partly due to the need for feeding the carry-out of the incrementer into the end-around-carry input of the adder in the prior art. This is necessary since during subtraction the incrementer input may be equal to “1 . . . 1” although the addend's exponent is larger than the product exponent, which usually cannot happen, i.e. in the absence of denormal numbers.
In prior art this situation is detected by checking the incrementer input for being equal to “1 . . . 1”, and if so activating the end-around-carry logic in the adder. Due to circuit speed and also due to physical distances of the components this becomes a more and more timing critical path. Also, since the all-1-detection finishes only shortly before the final incrementer and adder-output are available, the selection of the normalization shift amount becomes critical since it depends on the all-1-detection (compare FIG. 1).
The purpose of the invention is to develop a Floating Point Unit with fused multiply add, which is able of handling denormal multiplicand and addend operands in the regular data flow that can overcome the timing critical design by a sophisticated new method and design of a Floating Point Unit.